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1/17 l9362 september 2013 quad low-side driver for automo- tive application current feedback output for each power stage 5v supply voltage internal failure diagnostic output voltage slope control for low electro magnetic emissions internal short circuit protection overtemperature protection and overcurrent protection and disable switching frequency up to 2khz internal zener clamp of the output voltage for inductive loads parallel input spi for diagnostic information ex- change reset input typical internal oscillator fre- quency 325khz description the quad driver is an integrated quad low-side power switch with power limitation, load interrupt and shorted load detection, thermal shutdown, er- ror detection via spi interface and integrated z-di- odes for output clamping, free running diodes. powerso36 ordering number: l9362 quad low side driver block diagram 99at0007 s r = = driver trigger dv/dt control overtemp. i_scb filter t_scb non1 = = i_ol filter t_ol non1 = scg filter t_scg non1 failure register (fr) shift register fr reset reset reset = v cc ires = v cc = v cc v cc r ol reset reset 1 = oscillator osc under voltage reset v cc cfb1 cfb2 cfb3 cfb4 pgnd4 pgnd3 pgnd2 pgnd1 out4 out3 out2 out1 vcc = v cc non1 non2 non3 non4 sdi clk nsc sdo ires nres sgnd lgnd
l9362 2/17 pin connection pin functions pin no. pin name pin description notes 1 pgnd1 power ground 2n.c. 3 cfb1 output current feedback sinks current proportional to i out1 4 out1 output power switch 5 out1 output power switch 6 clk input clock digital input, schmitt trigger, internal pullup current 7 ncs inverted chip select input digital input, schmitt trigger, internal pullup current 8n.c. 9 sgnd signal ground 10 lgnd ground of digital part 11 n.c. 12 sdo serial data output digital tristate output 13 sdi serial data input digital input, schmitt trigger, internal pullup current 14 out4 output power switch 15 out4 output power switch 16 cfb4 output current feedback sinks current proportional to i out4 17 n.c. 18 pgnd4 power ground 19 pgnd3 power ground 20 n.c. 21 cfb3 output current feedback sinks current proportional to i out3 22 out3 output power switch 23 out3 output power switch 24 non4 inverted control signal input digital input, schmitt trigger, internal pullup current 99at0012 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 24 14 23 15 22 16 21 17 20 18 pgnd2 n.c. cfb2 out2 out2 non1 non2 n.c. vcc n.c. nres non3 non4 out3 out3 cfb3 n.c. pgnd3 frame connected to pgnd 19 pgnd1 n.c. cfb1 out1 out1 clk ncs n.c. sgnd lgnd n.c. sdo sdi out4 out4 cfb4 n.c. pgnd4
3/17 l9362 thermal data absolute maximum ratings for externally applied voltages or currents exceeding these limits damage of the circuit may occur note: the maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the ic will result. 25 non3 inverted control signal input digital input, schmitt trigger, internal pullup current 26 nres inverted reset input digital input, schmitt trigger, internal pullup current 27 n.c. 28 vcc 5v supply voltage input 29 n.c. 30 non2 inverted control signal input digital input, schmitt trigger, internal pullup current 31 non1 inverted control signal input digital input, schmitt trigger, internal pullup current 32 out2 output power switch 33 out2 output power switch 34 cfb2 output current feedback sinks current proportional to i out2 35 n.c. 36 pgnd2 power ground symbol parameter test conditions min. typ. max. unit thermal resistance r th j-case thermal resistance junction to case (one powerstage in use) die must be soldered on the frame. 4.5 c/w r thja thermal resistance junction-ambient pad layout 50 c/w r thja thermal resistance junction-ambient pad layout + 6 cm 2 on board heat sink 35 c/w esd esd mil 883c ? 2kv symbol parameter test conditions min. typ. max. unit supply voltages v cc supply voltage -0.3 7 v outputs (out 1 ... 4) v out continues output voltage with no reverse current. -0.3 45 v i outc continues current 3.0 a i scbpeak peak output current -10 i_scb a w off clamped energy at the switching off for 2ms, see fig. 8 50 mj inputs (nonx; ncs; clk; nres; sdi) v in input voltage -0.3 7 v outputs (sdo; cfb) v out output voltage -0.3 v cc +0.3 v operating junction temperature t j operating junction temperature -40 150 c pin functions (continued) pin no. pin name pin description notes
l9362 4/17 electrical characteristics 4.5v ? v cc ? 5.5v, -40c ? t j ? 125c, unless otherwise specified. symbol parameter test conditions min. typ. max. unit supply current i ccres standby current without load. t j ? 85c nres = low 1.3 ma i ccopm operating mode i out 1 ... 4 = 2a 11 17 ma i cclv low voltage supply current v cc < 0,5v 80 ? a inputs (nonx; ncs; clk; nres; sdi) v inl low threshold -0.3 0.2 ? v cc v v inh high threshold 0.7 ? v cc v cc +0.3 v v hyst hysteresis 0.85 v i in input leakage current v in = v cc 10 ? a i in input current (nonx, ncs, clk, sdi) v in ? 0.8 ? v cc 20 100 ? a i in nres input current nres 3 20 ? a serial data output v sdoh high output level (i sdo = -2ma) v cc - 0.4 v v sdol low output level (i sdo = 3.2ma) 0.4 v i sdol tristate leakage current (ncs = high; v sdo = 0v ... v cc ) -10 10 ? a outputs (out 1 ... 4) i outl1 leakage current 1 (non = high; v out = 14v; v cc = 5v) 10 ? a v clpa output clamp voltage v clpa (i out = 0.5a) 45 50 60 v w off clamped energy at the switching off 1) for 2ms, see fig. 8 50 mj r dson on resistance i out = 2a; t j = 150c; t j = 25c 2) 250 500 300 m ? m ? ovr p1 ovr p2 positive output voltage ramp (with inductive load) v out = 30% ... 80% of v bat =16v 3) v out = v bat ... 0.9 ? v clp 3) 0.3 0.75 0.9 1.35 2.25 v/ ? s v/ ? s ovr n negative output voltage ramp 80% ... 30% of v bat = 16v with inductive load 3) 0.3 0.9 1.35 v/ ? s t don turn on delay non = 50%; v out = 0.8 ? v bat 0410 ? s t doff turn off delay non = 50%; v out = 0.3 ? v bat 0410 ? s note 1: typical loads for the zener clamping and the output voltage ramps are: a) 10 ? , 16mh at all outputs or b) 25 ? , 160mh note 2: at 150c guaranteed by design and electrical characterisation note 3: tested with resistive load of r load = 50 ?
5/17 l9362 powerstage protection i scb short current detection and switch off threshold with filter-time t_scb. 3.0 5.0 a t_scb short circuit switch off delay time 3 30 ? s v ccmin v cc undervoltage 3.0 4.0 v current feedback t ratio 1 i cfb / i out for i out =0.4...2a 4) v cfb ? 1.8v 1.45 1.65 2 ma/a t mps1 6) 5) temperature stability for 0.4a to < 2.0a, related to 25c ? 3 ? 6% curs1 for i out = 0.4a to 2a 5) current stability ? gain/gain at 2a t j = -40c -12 17 % t j = +25c -6 10 % t j = +125c -5 5 % curlin1 6) curlin2 for i out = 0.4a to 1.0a 4) for i out = 1.0a to 2.0a 4) linearity error (within the calibration points at 0.5a, 1a, 2a) ? 0.2 ? 1 ? 0.7 % % note 4: at 150c guaranteed by design and electrical characterisation note 5: guaranteed by design and electrical characterisation note 6: values for t mps1 , curlin1 and curlin2 are typical values from testing results diagnostic v ref1 short to gnd threshold voltage for i out ? 2a 0.390 ? v cc 0.435 ? v cc v t_scg short to gnd filter time 140 250 ? s i ol open load threshold current 10 55 ma t_ol open load filter time 140 265 ? s r ol pullup resistor at out1, out2, out3 and out4 for ol detection 2.0 8.0 k ? t off temperature detection threshold 7) 155 170 190 c note 7: guaranteed by measurement and correlation electrical characteristics (continued) 4.5v ? v cc ? 5.5v, -40c ? t j ? 125c, unless otherwise specified. symbol parameter test conditions min. typ. max. unit
l9362 6/17 note: 8. input pin capacitance of sdi, clk, ncs, non1, non2, non3 , non4 6pf typical; output pin capacitance of sdo 12pf typica serial diagnostic link (external load capacitor at sdo = 100pf) f clk clock frequency 50% duty cycle. 0 3 mhz t clh minimum time clk = high 100 ns t cll minimum time clk = low 100 ns t pcld propagation delay clk to data at sdo valid. 100 ns t csdv ncs = low to data at sdo valid. 100 ns t sclch clk low before ncs low setup time clk to ncs change h/l. 100 ns t hclcl clk change l/h after ncs = low 100 ns t scld sdi input setup time clk change h/l after sdi data valid. 20 ns t hcld sdi input hold time sdi data hold after clk change h/l. 20 ns t sclcl clk low before ncs high 150 ns t hclch clk high after ncs high 150 ns t pchdz ncs l/h to output data float 100 ns t fncs ncs filter-time pulses ? t fncs will be ignored. 10 40 ns electrical characteristics (continued) 4.5v ? v cc ? 5.5v, -40c ? t j ? 125c, unless otherwise specified. symbol parameter test conditions min. typ. max. unit
7/17 l9362 1.0 diagnostic register and spi timing figure 1. impulse diagram to read the diagnostic register note: fr_reset means reset failure storage (internal signal) figure 2. diagnostic failure register structure fr_reset sdi lsb d1 d2 d3 d4 d5 99at0008 d6 msb d2 sdo clk ncs lsb fsl d1 d6 d4 d3 d5 msb 99at0009/a d5 d7 d6 d1 d3 d4 d2 d0 fsl msb lsb failure indicator bit (only valid during ncs = low to the first l to h clk change 1: failure stored 0: no failures status channel 4 d0 d1 status 1 1 no failures 1 0 open circuit, channel on 0 1 short to battery or overtemperature 0 0 short to gnd, channel off status channel 3 d2 d3 corresponding to d0 d1 status channel 2 d4 d5 corresponding to d0 d1 status channel 1 d6 d7 corresponding to d0 d1
l9362 8/17 figure 3. timing of the serial interface figure 4. short-circuit to gnd failure (scg-failure) detection sdi t scld t hcld d0 d1 d7 99at0010 t hclch t sclch t csdv sdo clk ncs t pcld fsl t clh t hclcl d0 t cll d7 t pchdz t sclcl 00at0002 t_scg (filter-time) failure-detection v drain v drain < v ref at off-state failure-store filter-time v ref non off on failure-detection time for a scg-failure scg-failure
9/17 l9362 figure 5. open-load failure (ol-failure) detection 00at0003 non off on failure detection active for a sporadical ol-failure lload i_ol lload > i_ol diagnostic active t_ol (filter-time) failure-detection failure-store sporadical failure-detection statical failure-detection t_ol retrigger t filter retrigger filter lload > i_ol for t > t_ol sporadical failure-detection t < t_ol
l9362 10/17 figure 6. different cases for an open load failure detection (case 1 to 10) 00at0004 case 10 failure register status output current case 9 failure register output current status case 8 case 7 current output failure register status case 6 failure register output current status case 5 failure register output current status failure register output current case 4 status case 3 current output failure register status failure register case 2 reset failure register non input case 1 status iol = ol filter time iol iol iol iol iol iol iol ol t non input output current iol t ol ol t ol t t ol t ol t ol ol t ol t ol t t ol ol t ol t ol t ol t t ol ol t output current failure register status iol ol t ol t ol t failure register status
11/17 l9362 figure 7. different cases for an open load failure detection (case 11 to 20) output current status failure register failure register reset non input case 20 failure register status output current case 19 failure register output current status case 18 case 17 current output failure register status case 16 failure register output current status case 15 failure register output current status failure register output current case 14 status case 13 current output failure register status failure register output current case 12 status failure register output current case 11 status iol iol iol iol iol iol iol iol iol ol t ol t ol t ol t ol t ol t ol t ol t t ol t ol t ol t ol t ol t ol ol t ol t ol t ol t t ol t ol t ol ol t ol t ol t ol t ol t 00at0005 iol
l9362 12/17 figure 8. max clamp energy specification figure 9. tratio of current feedback output versus output current 0 200 400 600 800 1000 0.0 2.0 4.0 6.0 8.0 10.0 energy/[mj] pulse width/[ms] temp=25?c temp=150?c 1.30e-03 1.35e-03 1.40e-03 1.45e-03 1.50e-03 1.55e-03 1.60e-03 1.65e-03 1.70e-03 1.75e-03 1.80e-03 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 tratio iout/[a] temp=-40?c temp=-20?c temp=25?c temp=70?c temp=150?c
13/17 l9362 figure 10. tmps1 vs. temperature (4.5v ? v cc ? 5.5v; 0.5a ? i out1...4 ? 3a) . functional description introduction the quad low side driver uf07 is built up of four identical channels (low side drivers), controlled by four cmos input stages. each channel is protected against short to v bat and by a zener clamp against overvoltage. a diagnostic logic recognizes four failure types at the ou tput stage: overcurrent, short to gnd, open-load and overtemperature. the failures are stored individually for each channel in one byte which can be read out via a serial interface (spi). each channel has a current feedback output which sinks a current proportional to the load current of the low side switch. output stage control each of the four output stages is switched on and off by an individual control line (non-input). the logic level of the control line is cmos compatible. the output transistors are switched off when the inputs are not connected. power transistors each of the four output stages has its own zener clamp. this causes a voltage limitation at the power transistors when inductive loads are switched off. output voltage ramp occurring when the output is switched on or off, is within defined limits. output transistors can be connected in parallel to increase the current capability. in this case, the associated inputs, outputs and current feedback outputs should be connected together. diagnostics following failures at the output stage are recognized: short circuit to v bat or overtemp................= scb (highest priority) short circuit to gnd...................................=scg open load.................................................= ol (lowest priority) -3 -2 -50 0 tmps1/[%] temp./[?c] 50 100 150 200 -1 0 1 2 3
l9362 14/17 short-circuit and overtemperature protection (scb) if the output current increases above the short current limit for a longer time than t_scb or if the temperature increases above t off , then the power transistor is immediately switched off. it remains switched off until the control signal at the non-input is switched off and on again. this filter time has the purpose to suppress wrong detection on short spikes. all four outputs have an independent overtemperature detection and shutdown. this measurement is active while the powerstage is switched on. the short circuit detection and the overtemperature detect ion are using the same bit in the diagnostic (one for each channel). a scg failure will be recogniz ed, when the drain vo ltage of the output stage is lo wer as the ?short cut to ground threshold voltage?, while the output stage is switched off (see fig. 4). the scg failure is filtered with a digital filter (t_scg) to suppress the storage of a failure at small scg spikes, which are typical during the transition of the power output. this filter is triggered by the non input and the (analog) scg detection. if the current through the output stage is lower than the iol-reference, then an ol failure will be recognized after a filter time. this measurement is active while the powerstage is switched on. the open load failure detection has 2 different modes, the statical failure detection and the sporadic failure detection. one main difference is, that a statical failure is transferred to the failure register with the next rising edge of non, whereas a sporadic failure is transferred immediately to the failure register (see fig. 5, 6 and 7). in both failure modes the ol detection is filtered (t_ol=t ol ) and is using together with the scg detection the same digital filter for suppression of spikes. the failures are stored regarding to their priority (see above). a failure with a higher priority overwrites an even- tually already detected failure with a lower priority. diagnostic interface the communication between the microprocessor and the failure register runs via the spi link. if there is a failure stored in the failure register, the first bit of the shift register is set to a high level. with the h/l change at the ncs pin the first bit of the diagnostic shift register will be tr ansmitted to the sdo output. the sdo output is the serial output from the diagnostic shift register and it is trista te when the ncs pin is high. the clk pin clocks the diag- nostic shift register. new sdo data will appear on every rising edge of the clk pin and new sdi data will be latched on every falling edge into the shift register. with t he first positive pulse of the clk the contents of the failure register is copied to the spi shift register and a internal reset (fr_reset) is generated. this internal reset clears the failure register and thus the failure register is capable of detecting failures also during the spi read cycle. there is no bus collision at a small spike at the ncs. the clk has to be low, while the ncs signal is changing. current feedback each channel has a current feedback output which sinks a current proportional to the load current of the low side switch. using this output servo loop applications can be realized by applying a pwm signal to the non input. a typical diagram of the current feedback output at different temperatures is shown in figure 9.
15/17 l9362 reset there are two different reset functions realized: undervoltage reset as long as the voltage of vcc is lower than v ccmin , the powerstages are switched off, the failure register is reset and the sdo output remains tristate. external reset as long as the nres pin is lo w following circuits are reset: powerstages failure register and the sdo output is tristate. undervoltage protection at vcc below v ccmin the device remains switched off even if there is a voltage ramp at the out pin. figure 11. application circuit v cc r ol reset reset reset 1 under voltage reset v cc 99at0011 s r = = driver trigger dv/dt control overtemp. i_scb filter t_scb non1 = = i_ol filter t_ol non1 = scg filter t_scg non1 failure register (fr) shift register fr reset = v cc ires = v cc = v cc reset = oscillator osc cfb1 cfb2 cfb3 cfb4 v cc adc pgnd4 pgnd3 pgnd2 pgnd1 out4 out3 (optional for all channels) out2 out1 c 1 c 2 c 3 c 4 vcc c2 v cc c1 non1 = v cc non2 non3 non4 c sdi clk nsc sdo ires v s nres sgnd lgnd
l9362 16/17 outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 3.60 0.1417 a1 0.10 0.30 0.0039 0.0118 a2 3.30 0.1299 a3 0 0.10 0.0039 b 0.22 0.38 0.0087 0.0150 c 0.23 0.32 0.0091 0.0126 d 15.80 16.00 0.6220 0.6299 d1 9.40 9.80 0.3701 0.3858 e 13.90 14.5 0.5472 0.5709 e1 10.90 11.10 0.4291 0.4370 e2 2.90 0.1142 e3 5.80 6.20 0.2283 0.2441 e 0.65 0.0256 e3 11.05 0.4350 g 0 0.10 0.0039 h 15.50 15.90 0.6102 0.6260 h 1.10 0.0433 l 0.8 1.10 0.0315 0.0433 n 10? (max) s 8? (max) note: ?d and e1? do not include mold flash or protusions. - mold flash or protusions shall not exceed 0.15mm (0.006?) - critical dimensions are "a3", "e" and "g". powerso-36 0096119 c
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